Signal speeds associated with integrated circuit devices may be subject to both inter-chip variation and on-chip variation. Inter-chip variation, or differing speeds among integrated circuit devices in a system, has been a noted concern in the integrated circuit industry. As a result, various techniques have been developed for determining and compensating for inter-chip variation. However, on-chip variation (OCV), or differing signal path speeds in an individual integrated circuit device, is a relatively new concern for application-specific integrated circuit (ASIC) vendors and fabricators.
In order to determine OCV of signal paths of an integrated circuit device, simulated timing delays of the signal paths may be modeled with the use of a timing analysis tool. OCV typically results from both cell and wire delays of the integrated circuit device, however, an integrated circuit device may produce wire delays that are less than 1% of the critical path delay. This percentage of the critical path delay may be determined by a simple script running over timing path reports. Thus, OCV determination techniques may ignore the portion of OCV that is attributable to wire delay.
In modeling signal path delays, ASIC vendors and fabricators typically provide “worst-case fast” and “worst-case slow” simulated timing delay models. For example, cells in a signal path will never be faster than the worst-case fast model, or slower than the worst-case slow model. The determined OCV factor may be added to a signal path of the integrated circuit device in various ways, which are known to those skilled in the art.
As the size and complexity of an integrated circuit device increases, the resulting magnitude of OCV also increases. For example, a 20×20 millimeter chip with 5000 cell rows has an increased chance of having cells in the integrated circuit device operating at different speeds. A larger chip also has an increased chance of its signal paths being affected by process, voltage, temperature (PVT) factors, which may vary across the surface of an integrated circuit device.
Process variation may be caused by the optical proximity effect, which occurs during optical lithography and results in systematic line width variations across the chip. Process variation may also be caused by aberrations in the optical system of the wafer stepper. Process variation also has two main effects: variation in the effective gate length, and variations in wire resistivity and geometry. These effects thereby result in changes in the speed of a signal path. Regarding voltage variation across a chip surface, static voltage drop (IR drop) is commonly modeled in the industry, for example, using a software program known as Astro-Rail™, commercially available from Synopsis, Inc., California, USA. However, voltage and process variation are complex, and remain a domain for specialists in the integrated circuit industry. See, for example, D. Chinnery et al., “Closing the Gap between ASIC and Custom,” Kluwer, 2002. Furthermore, real data about the size of PVT factors is often proprietary, hard to come by, or both.
Commonly, in order to determine an OCV factor for each signal path, the timing analysis tool is run at a single worst case PVT point. However, due to the fact that PVT factors vary across the integrated circuit device, using an OCV factor computed from a single PVT point is unduly pessimistic, and can significantly increase project time, and thus development costs. Much of the delay resulting in OCV depends on the distances between the cells involved; for example, there is less of a delay if the cells are close together, more if they are far apart. Assuming a worst case variation of PVT factors for purposes of fabrication, as described above, may lead to signal path delays large enough to seriously disrupt an ASIC project schedule.
Thus, a need exists for improved techniques for determining an OCV factor that takes into account the effects of varying PVT factors across the surface of the integrated circuit device.